The present invention generally relates to a memory controller for a flash memory, a flash memory system having the memory controller, and a method of controlling the flash memory.
As described in Reference 1 (JP-A-2003-233529), a storage apparatus employing a flash memory as a storage medium has a buffer memory in which data read from the flash memory and data to be written to the flash memory, so as to absorb a difference between an operating speed of a host system and that of the flash memory, or a difference between an access speed of a host system and a writing (programming)/reading speed of the flash memory.
Further, in the storage apparatus, it is general to write data in parallel to the plurality of flash memories and read data in parallel from the plurality of flash memories so as to improve a substantial access speed to the storage apparatus. For example, the following memory access technique is described in Reference 2 (WO 2002/046929). In the memory access technique, virtual blocks are formed by virtually combining a plurality of physical blocks each included in each of flash memories, and data writing to the virtual block and data reading therefrom are performed. Therefore, data are written in parallel to the flash memories and data are read in parallel therefrom.